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Hello guys, Today we will see what is the difference between m_sequencer and p_sequencer, may be this is the most frequently asked question in interview from uvm section and may be this is the most confusing topic too. Let's today solve this puzzle forever. Here I am assuming that you are aware about uvm components and uvm object. Basically sequencer is used to route the random transactions to driver which is generated by sequence class. If you are not specifying any thing by default uvm is using m_sequencer.      WHY WE NEED P_SEQUENCER ?????? Say you want to design your sequence class such that based on RTL response it should generate further transactions. In this scenario sequence needs to access  the user defined properties or methods of the sequencer as per requirement of the project which are unavailable in m_sequencer. So in this scenario you need to use p_sequencer. Basically it overrides the actual sequencer and now you can use p_sequencer...

Hello guys, Today we are going to learn that why we actually required virtual sequencer to have in our environment and how we can implement virtual sequencer in our environment using two different methods. Why Virtual Sequencer?????   A virtual sequence is a sequence which controls stimulus generation using several sequencers. In UVM architecture, sequences, sequencers and drivers are focused on point interfaces and  hence there needs to be a higher layer sequence to coordinate stimulus generation across different interfaces and the interactions between them which is what a virtual sequence is.  A virtual sequencer is a uvm_sequencer which contains the handles of all the target sequencers  focused on each point interface.  A virtual sequence can be started on a virtual sequencer and the virtual sequence can generate and run sub-sequences on target sequencers in a coordinated manner.    Usage of virtual sequencer is a conveni...

Hello guys, As we all know assertion samples the values in pre pond region. Most of us are suffering to write assertion because of this issue as we are very comfortable with actual simulation time. Here we are going to learn how to sample the value of the signal in current time for assertion. We will also learn how to sample rise and fall of signal in current time. Problem we face while writing assertion : Say I want to check my input signal rising edge should be there on posedge or negedge of clock. Demo_Code :   property my_p;   @ (posedge clock or negedge clock)    $rose(input); endproperty If I simply write my property like above I will not be able to capture any rising edge of input as for assertion sampling is done in pre pond region as we can see in above figure. It will always sample 0 instead of 0 to 1 transition. SOLUTION :   ASSUMPTION : CLK is having period of 100ns. 1) I want to check my signal A should be 1 or 0 on posedge ...

Hello friend, In this blog we are going to discuss about the cross auto bin max. ex. bit [3:0] a; bit [3:0] b; A_C : coverpoint a_c {    bin1 = bins[7:0];    bin2 = bins[7:15];  } B_C : coverpoint b_c {    bin1 = bins[7:0];    bin2 = bins[7:15];  } i)  A_B_CROSS : cross a_c , b_c; ii) A_B_CROSS : cross a , b; In first case we are doing cross coverage of to coverpoints where in second case two variables. In first case four cross bins will be generated as each cover point is having two two bins where in second case (2^4 * 2^4) = 256 bins will be generated. This happens because for simple coverage auto_bin_max value is 64 where cross_auto_bin_max is infinite for cross coverage. So say if you have declared two vars as int and then you are directly performing their cross coverage then (2^32 * 2^32) bins will be generated because cross_auto_bin_max value is infinite. If you are just performing simple covera...

Hello friends, In this blog We are going to  see a very useful feature of  bind in system verilog. You can use the following eda link as a reference for this blog. https://www.edaplayground.com/x/5_zJ Module hierarchy : top_DUT       | top_DUT_in       |   DUT       |  in_DUT Here as shown above top_DUT is my top most module which contain top_DUT_in. DUT is instantiated in top_DUT_in. Where as in_DUT is instantiated in DUT. Now this top most design module top_DUT is instantiated in testbench. Using bind method we have bind interface with DUT module using hierarchical reference. Now here comes the magic trick. In interface class use the signals of DUT module as you have bind this module with interface even more you are also eligible for using up and down hierarchical module's signal of DUT using theier instance name in same interface. Means just by connecting one module of the module hier...

Use the below eda link as a reference : https://www.edaplayground.com/x/5fXJ Why to override ?????? For example: In your environment, you have a driver component. You would like the extend the driver component for error injection scenario. After defining the extended driver class with error injection, how will you replace the base driver component which is deep in the hierarchy of your environment ? Using hierarchical path, you could replace the driver object with the extended driver. This could not be easy if there are many driver objects. Then you should also take care of its connections with the other components of testbenchs like scoreboard etc.  Using the uvm fatroy, it is very easy to solve the above requirements. Only class extended from uvm_object and uvm_component are supported for this. There are three basic steps to be followed for using uvm factory. 1) Registration     While defining a class , its type has to be registered with th...