Bind Gotchasss

Hello friends,
In this blog We are going to  see a very useful feature of  bind in system verilog.
You can use the following eda link as a reference for this blog.
https://www.edaplayground.com/x/5_zJ


Module hierarchy :

top_DUT
      |
top_DUT_in
      |
  DUT
      |
 in_DUT

Here as shown above top_DUT is my top most module which contain top_DUT_in. DUT is instantiated in top_DUT_in. Where as in_DUT is instantiated in DUT.
Now this top most design module top_DUT is instantiated in testbench.
Using bind method we have bind interface with DUT module using hierarchical reference.

Now here comes the magic trick. In interface class use the signals of DUT module as you have bind this module with interface even more you are also eligible for using up and down hierarchical module's signal of DUT using theier instance name in same interface. Means just by connecting one module of the module hierarchy to the interface using bind method you can use any of the up or down module of this hierarchy in your interface.

In SV LRM it is said that you can use up hierarchy if you are using bind method but here we have explored that even we can also use down hierarchy of that connected module using bind method.

See above eda link for further practical under standing.
This is verified on vcs as well as cadence tool.

Enjoy the bind method as per your convenience.

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