HOW TO SAMPLE VALUES IN CURRENT TIME FOR ASSERTIONS

Hello guys,
As we all know assertion samples the values in pre pond region. Most of us are suffering to write assertion because of this issue as we are very comfortable with actual simulation time. Here we are going to learn how to sample the value of the signal in current time for assertion. We will also learn how to sample rise and fall of signal in current time.

Problem we face while writing assertion :


Say I want to check my input signal rising edge should be there on posedge or negedge of clock.

Demo_Code : 

property my_p;
  @ (posedge clock or negedge clock) 
  $rose(input);
endproperty

If I simply write my property like above I will not be able to capture any rising edge of input as for assertion sampling is done in pre pond region as we can see in above figure. It will always sample 0 instead of 0 to 1 transition.

SOLUTION :

 ASSUMPTION : CLK is having period of 100ns.

1) I want to check my signal A should be 1 or 0 on posedge of CLK.


 DEMO_CODE :

  event e;

   always @ (posedge CLK) begin
    1ns;
    -> e ;
  end

 property my_p;
  @ (e)
  1 |-> (A | !A);
endproperty

 MY_P : assert property (my_p);

Here I am doing sampling on event e which is triggered on 1ns delay with posedge of CLK. By doing this we are making sure that our sampling of signal happens in current simulation time rather in pre pond region. 1 means always true so on triggering of that event my assertion will check for value of A should be either 1 or 0.

2) I want to check my signal i_a should have rising  edge on posedge of sig_clk.


DEMO_CODE :

  event assert_e;
wire  assert_signal_dummy;

 assign #1ns assert_signal_dummy = i_a;

   always @ (posedge sig_clk) begin
    1ns;
    -> assert_e ;
  end

 property my_p;
  @ (assert_e)
  1 |->  ( i_a  &&  ! assert_signal_dummy );
endproperty

 MY_P : assert property (my_p);


Waveforms :



Here we have taken extra wire assert_signal_dummy for checking the rise in signal i_a. We are assigning i_a to assert_signal_dummy with 1ns delay. Now as we know our sampling for assertion is happening on 1ns delay so we are getting actual signal value ie. i_a will be sampled at 769ns as value 1 where assert_signal_dummy will be sampled as 0 here as we can see in the diagram so basically it show we are having positive edge of i_a at 768ns.

3) I want to check my signal i_a should have falling  edge on posedge of sig_clk.


DEMO_CODE :

 event assert_e;
wire  assert_signal_dummy;

 assign #1ns assert_signal_dummy = i_a;

   always @ (posedge sig_clk) begin
    1ns;
    -> assert_e ;
  end

 property my_p;
  @ (assert_e)
  1 |-> ( ! i_a  &&  assert_signal_dummy );
endproperty

 MY_P : assert property (my_p);


Waveforms :




 NOTE : Here for generating an event I have used 1ns delay because I am assuming my timescale is 1ns/1ps. You can change that value as per your requirement of clock period and time scale.

Hope this article will be helpful to you guys to develop  assertions in some easier way.

Comments

Post a Comment

Popular posts from this blog

'WITH' Operator in SV Coverage

Hello guys, Today we are going to see how we can use 'with' operator which is there in sv coverage. Many of us are writing coverage for our projects. I think most of us are under using the use of 'with' operator  in sv coverage. So lets explore one rarely explored feature which is already available for us in sv coverage. SV LRM DESCRIPTION : The with clause specifies that only those values in the covergroup_range_list that satisfy the given expression (i.e., for which the expression evaluates to true, as described in 12.4) are included in the bin. In the expression, the name item shall be used to represent the candidate value. The candidate value is of the same type as the coverpoint. The name of the coverpoint itself may be used in place of the covergroup_range_list to denote all values of the coverpoint. Only the name of the coverpoint containing the bin being defined shall be allowed; no other coverpoint names shall be permitted. Consider the following exa...
Read more

Difference Between m_sequencer and p_sequencer

Image
Hello guys, Today we will see what is the difference between m_sequencer and p_sequencer, may be this is the most frequently asked question in interview from uvm section and may be this is the most confusing topic too. Let's today solve this puzzle forever. Here I am assuming that you are aware about uvm components and uvm object. Basically sequencer is used to route the random transactions to driver which is generated by sequence class. If you are not specifying any thing by default uvm is using m_sequencer.      WHY WE NEED P_SEQUENCER ?????? Say you want to design your sequence class such that based on RTL response it should generate further transactions. In this scenario sequence needs to access  the user defined properties or methods of the sequencer as per requirement of the project which are unavailable in m_sequencer. So in this scenario you need to use p_sequencer. Basically it overrides the actual sequencer and now you can use p_sequencer...
Read more

Cross Auto Bin Max

Hello friend, In this blog we are going to discuss about the cross auto bin max. ex. bit [3:0] a; bit [3:0] b; A_C : coverpoint a_c {    bin1 = bins[7:0];    bin2 = bins[7:15];  } B_C : coverpoint b_c {    bin1 = bins[7:0];    bin2 = bins[7:15];  } i)  A_B_CROSS : cross a_c , b_c; ii) A_B_CROSS : cross a , b; In first case we are doing cross coverage of to coverpoints where in second case two variables. In first case four cross bins will be generated as each cover point is having two two bins where in second case (2^4 * 2^4) = 256 bins will be generated. This happens because for simple coverage auto_bin_max value is 64 where cross_auto_bin_max is infinite for cross coverage. So say if you have declared two vars as int and then you are directly performing their cross coverage then (2^32 * 2^32) bins will be generated because cross_auto_bin_max value is infinite. If you are just performing simple covera...
Read more