Lets Fly Towards The Ultimate Happiness Of Knowledge

Hello guys, Today we are going to see how we can use 'with' operator which is there in sv coverage. Many of us are writing coverage for our projects. I think most of us are under using the use of 'with' operator  in sv coverage. So lets explore one rarely explored feature which is already available for us in sv coverage. SV LRM DESCRIPTION : The with clause specifies that only those values in the covergroup_range_list that satisfy the given expression (i.e., for which the expression evaluates to true, as described in 12.4) are included in the bin. In the expression, the name item shall be used to represent the candidate value. The candidate value is of the same type as the coverpoint. The name of the coverpoint itself may be used in place of the covergroup_range_list to denote all values of the coverpoint. Only the name of the coverpoint containing the bin being defined shall be allowed; no other coverpoint names shall be permitted. Consider the following exa...

Hello guys, Today we will see what is the difference between m_sequencer and p_sequencer, may be this is the most frequently asked question in interview from uvm section and may be this is the most confusing topic too. Let's today solve this puzzle forever. Here I am assuming that you are aware about uvm components and uvm object. Basically sequencer is used to route the random transactions to driver which is generated by sequence class. If you are not specifying any thing by default uvm is using m_sequencer.      WHY WE NEED P_SEQUENCER ?????? Say you want to design your sequence class such that based on RTL response it should generate further transactions. In this scenario sequence needs to access  the user defined properties or methods of the sequencer as per requirement of the project which are unavailable in m_sequencer. So in this scenario you need to use p_sequencer. Basically it overrides the actual sequencer and now you can use p_sequencer...

Hello guys, Today we are going to learn that why we actually required virtual sequencer to have in our environment and how we can implement virtual sequencer in our environment using two different methods. Why Virtual Sequencer?????   A virtual sequence is a sequence which controls stimulus generation using several sequencers. In UVM architecture, sequences, sequencers and drivers are focused on point interfaces and  hence there needs to be a higher layer sequence to coordinate stimulus generation across different interfaces and the interactions between them which is what a virtual sequence is.  A virtual sequencer is a uvm_sequencer which contains the handles of all the target sequencers  focused on each point interface.  A virtual sequence can be started on a virtual sequencer and the virtual sequence can generate and run sub-sequences on target sequencers in a coordinated manner.    Usage of virtual sequencer is a conveni...

Hello guys, As we all know assertion samples the values in pre pond region. Most of us are suffering to write assertion because of this issue as we are very comfortable with actual simulation time. Here we are going to learn how to sample the value of the signal in current time for assertion. We will also learn how to sample rise and fall of signal in current time. Problem we face while writing assertion : Say I want to check my input signal rising edge should be there on posedge or negedge of clock. Demo_Code :   property my_p;   @ (posedge clock or negedge clock)    $rose(input); endproperty If I simply write my property like above I will not be able to capture any rising edge of input as for assertion sampling is done in pre pond region as we can see in above figure. It will always sample 0 instead of 0 to 1 transition. SOLUTION :   ASSUMPTION : CLK is having period of 100ns. 1) I want to check my signal A should be 1 or 0 on posedge ...