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Hello friend, In this blog we are going to discuss about the cross auto bin max. ex. bit [3:0] a; bit [3:0] b; A_C : coverpoint a_c {    bin1 = bins[7:0];    bin2 = bins[7:15];  } B_C : coverpoint b_c {    bin1 = bins[7:0];    bin2 = bins[7:15];  } i)  A_B_CROSS : cross a_c , b_c; ii) A_B_CROSS : cross a , b; In first case we are doing cross coverage of to coverpoints where in second case two variables. In first case four cross bins will be generated as each cover point is having two two bins where in second case (2^4 * 2^4) = 256 bins will be generated. This happens because for simple coverage auto_bin_max value is 64 where cross_auto_bin_max is infinite for cross coverage. So say if you have declared two vars as int and then you are directly performing their cross coverage then (2^32 * 2^32) bins will be generated because cross_auto_bin_max value is infinite. If you are just performing simple covera...

Hello friends, In this blog We are going to  see a very useful feature of  bind in system verilog. You can use the following eda link as a reference for this blog. https://www.edaplayground.com/x/5_zJ Module hierarchy : top_DUT       | top_DUT_in       |   DUT       |  in_DUT Here as shown above top_DUT is my top most module which contain top_DUT_in. DUT is instantiated in top_DUT_in. Where as in_DUT is instantiated in DUT. Now this top most design module top_DUT is instantiated in testbench. Using bind method we have bind interface with DUT module using hierarchical reference. Now here comes the magic trick. In interface class use the signals of DUT module as you have bind this module with interface even more you are also eligible for using up and down hierarchical module's signal of DUT using theier instance name in same interface. Means just by connecting one module of the module hier...

Use the below eda link as a reference : https://www.edaplayground.com/x/5fXJ Why to override ?????? For example: In your environment, you have a driver component. You would like the extend the driver component for error injection scenario. After defining the extended driver class with error injection, how will you replace the base driver component which is deep in the hierarchy of your environment ? Using hierarchical path, you could replace the driver object with the extended driver. This could not be easy if there are many driver objects. Then you should also take care of its connections with the other components of testbenchs like scoreboard etc.  Using the uvm fatroy, it is very easy to solve the above requirements. Only class extended from uvm_object and uvm_component are supported for this. There are three basic steps to be followed for using uvm factory. 1) Registration     While defining a class , its type has to be registered with th...

QUERY : What if in top module I declare two variable with same name and pass them as an arguement to some task????? CODE : module top;   class aa;     task disp(int a,real b);       $display("INT a is ",a);       $display("REAL b is ",b);     endtask   endclass   initial begin     int a=5;     real a=10;        aa a1 = new;     a1.disp(a,a);   end endmodule CONCLUSION :  In  module which ever variable you defined first will go as both first and second arguement for disp.  QUERY : Say in my class all vars are rand and now I want to randomize only one var how to generate this scenario????? There are multiple ways you can do this. In test make rand_mode 0 for whole class object and then make rand_mode 1 for that particular variable.  Use  object.ranomize() method...